Subject: Re: Pinout for SED9421
From: shoppa_classiccmp at
trailing-edge.com (Tim Shoppa)
Date: Fri, 25 Nov 2005 09:31:03 -0500
To: cctalk at
classiccmp.org
FYI:the average PLL is a bear to build and debug,
they required clean
power and good board layout with ample groundplanes. The digital ones are
very good, simple to layout and shift rates with only a mux.
Allison
Don't neglect: PLL's require analog components of rather tight tolerances
to give consistent behavior from time-to-time and unit-to-unit.
That falls in the catagory of a bear to build part.
The digital data separator (I heard its designer once
refer to it as
a "jerk-locked-loop") has no such tight tolerances and in fact is usually
driven from a crystal oscillator.
That is a good description. It also depends on the number of bits used
as to how locked it is. Really only makes a difference when the peak shift
is bad due to impropper media or bad write precomp or the drive speed is
really off. Usually fixing the drive speed is easiest. The upside is
predictable performance and repeatability.
The one-shot-with-critical-RC-constant used in early FM
data separators
is a good example. With a little tweaking it really works pretty well.
But imagine mass-producing such a beast and training the assembly line
people to do the tweaking, as well as field service, as well as ...
(Of course us hackers don't mind!)
I hate analog oneshots unless they are timing uncritical. I worked with
an engineer that did everything with onshots and his stuff was prone to
wandering off or plain quitting.
The all time worst was the 1771 internal data sep. Tandy initally did that
to save parts. Really bad.
Allison