26 Oct
1999
26 Oct
'99
2:42 p.m.
> I do not accept your assertion, simply because you
asserted it(!).
Of course not. Nor am I compelled to do your homework
for you.
Whoa! You make an assertion, and -I- have to disprove it? Yow!
> Relevance to old iron? Because old iron had lots
of busses, new ones don't.
> Why is that?
Because it isn't the case. For example, the E4500
and its ilk have
multiple busses (mezzanine busses on the CPU and I/O board, I believe
built around Sun's UPA switch, in addition to the Gigaplane main bus,
which in and of itself has multiple buses, at least in the case
of the Starfire's Gigaplane-XB bus). Other examples include the
Cray/whatever 6400 SMP, Pyramid Nile, Sequent S5000 and I suspect
the SGI Challenge and HP T500, although I'd have to check. I
suppose the Sequent (or do they call themselves IBM now) NUMA/
NUMA-Q architecture is multiple bus as well, but not in the
sprit of what you've been discussing.
In my mind, at least, such machines don't qualify
as "old iron" :-)
Still seems to me that the busses break down into "few", that is,
Memory, Fast I/O, and Slow I/O.
I can understand a separate Memory and I/O bus (different speeds) ONLY
if the I/O devices can't run at memory speeds. (And, DRAM memory is, after
all, "L3 cache" if you will...).
What I see is that the earliest iron had few "channels" (busses) and then
during the computer baroque period (of which the vax is the prime example)
busses exploded, and now, there is a bus consolidation. For example, the PC
has two primary busses AGP and PCI (we will conveniently ignore memory
busses because memory subsystems must be tightly coupled to the processor
for decent performance).
But I'm not going to talk any more about this subject until somebody comes up
with data to support these architectural features, or until some references
I've been recommended come in.
But I find the history of computer bus architectures absolutely fascinating!
-mac