6 Jun
2002
6 Jun
'02
5:34 p.m.
I'm building a 6800 machine right now and I was
wondering about this "Halt and Catch on Fire"
instruction. Is this for real. This is a serious
question. Is there actually an instruction that will
overheat the chip?
--- Ben Franchuk <bfranchuk(a)jetnet.ab.ca> wrote:
Richard Erlacher wrote:
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One of the more interesting features of the 6502
is that when you're looking
at the data bus, it shows you what last was on
the
bus in those cases where
there's nothing present to drive the data-in
bus.
This will give you
information useful in figuring out what is going
inside the chip, and, that's
what gave me the clues that convinced me that the
reason the 6502 is so cheap
on silicon is that it doesn't use counters
for its
registers, but, rather,
uses simple gated latches and uses the ALU to
operate on the addresses during
phase-2 while operating on the data during
phase-1.
If you look at what's required to build a
synchronous counter large enough to
support the simple register set in the 6502
you'll
see that the saved gates
are sufficient to warrant its design in exactly
that way, and that it would
yield a significant savings in silicon. It
allows
you to use a relatively
complex ALU, together with a register set
that's
essentially a small RAM array
with an instruction set that never operates on
two
registers in a single
cycle. If you build the PC, the address bus
registers, the SP, the two index
registers, and the accumulator as 8-bit
registers,
it's easy to see why one
would do things that way. I'm not sure
anybody
has ever taken a really close
look at what happens when each possible opcode is
fed to the 6502 as the first
instruction after a reset and then recorded what
the CPU does with it right up
to the next SYNC, signalling that a new opcode is
being fetched, but it might
be a useful extension on what's been done.
Of
course, the 6502 is of little
interest to persons planning any practical
endeavors, so this fits squarely
under the aegis of this forum.
I think that the 6100 (PDP-8 on a chip) fit this
model better.
8 bit cpu's often used random logic thus don't cares
and unimplimented
opcodes
could change actions between cpu mask revisions.
Other than the 6800
HCF
instruction ( Halt and Catch on Fire ) most
undefined instructions
are mostly harmess.
--
Ben Franchuk - Dawn * 12/24 bit cpu *
www.jetnet.ab.ca/users/bfranchuk/index.html