Sometimes the data sheets for an SARM (or
whatever) indicate the=20
row/column structure. Not that it matters, I've not come across an SRAM=20
that has, say, faster access time from a change in row address than a=20
change in column address
When I once asked why there were so many different PDP-11 memory diagnostic=
s,
(beyond just unmapped vs mapped vs whatever processor diffs) I was
told that it was because each was structured to hit the row/column drivers
and induce known pattern-sensitive failure modes particular to the
core stack or chips in use.
I wonder...
For core it makes a lot of sense. Firstly to identify which driver has
failed (so you cna repair it), and secondly (and more importantly)
because there certainly are 'worst case' patterns which will check for
interaction between the drivers nad the like.
But does it still make sense for semiconductor memory? Are there
worst-case read/write sequences for SRAM or DRAM? I've certainly never
seen a data sheet which mentions them.
-tony