Hi,
I'm working on an Z80 MP/M II server for my 8080 CP/M computer and I
have been designing a MMU for it. I thought I'd post it here because it
could be useful to other builders or better still to talk about any
flaws or improvements.
The circuit diagram is here:
http://kaput.homeunix.org/~thrashbarg/MMU.png
Configured like that it is capable of accessing 256kB of RAM with write
protection, or 512kB without write protection by using the 'Mem WE'
output as an address line. The logical address range is divided up into
2kB pages, where those pages can be of any 2kB page in the physical
address range. It's more of a Memory Mapping Unit than a Memory
Management Unit.
MP/M II needs to remain resident in the highest 13kB of RAM so having
the write protection will prevent any runaway processes from crashing
the system. 50kB of RAM can be made available to the running program.
Pages can be duplicated in the logical address range, so if a process
only uses say 4kB of RAM only three pages need to be allocated to it,
two for the program itself and one to fill the rest of memory. There may
be a need to have a table on disk to tell the OS how many pages to
allocate, because a program may use less space on disk than what it
requires in memory.
The Process ID is determined by the 74174 to the left of the SRAM. When
the process changes the 2kB bank making the switch must not change or
the program will be moved and probably crash. In MP/M II this wont be an
issue because the system bank isn't supposed to move.
In this configuration there is a total of 64 processes, 63 if you don't
include the system as a process. When an interrupt occurs it clears the
PID register to zero so the system can be called to service the
interrupt request.
The 74175 to the far left controls the MMU and ROM. The ROM is enabled
after a reset and the MMU is disabled. This is done by deactivating the
left CS of the RAM and connecting the upper address bits of the CPU
directly to memory. The remaining two or three address lines should be
tied high with resistors, or even connected to the 74LS244 with those
inputs tied to +5 or Ground.
The tricky element is the 2kB dual port SRAM. I found two of them on an
old arcade game board. This lets the CPU program the mapping of memory
without having to implement a messy multiplexing system.
To program a bank an 11-bit address is loaded into ports F9h and FAh,
then the desired bank is programmed to port F8h. The lowest 5 bits of
the address selects the desired 2kB page the CPU will access and the
remaining 6 digits determine the PID. Maybe they should be split up so
one port selects the page and the other selects the PID.
Maybe someone can use this? I haven't looked deeply into the MP/M II
XIOS requirements so I may have left something out that it needs so is
anyone familiar with the XIOS?
Cheers,
Alexis.