I am not much
of a programmer, I'd be happy to help out where I can.
How about an AVR-based box (open, no BGAs, etc) perhaps with an SD
socket or CF socket, with an HPIB interface that will work with a)
"real" IEEE-488 hosts and b) PET/CBM hosts which are electrically
GPIB/IEEE-488, but might have some "Commodoreisms" when it comes to
timing and throughput and such since they are implemented as 6502 code
wiggling PIA and/or VIA I/O lines?
Once you have a platform that is electrically and timing-compatible
with HPs and PETs, it shouldn't matter if you choose to implement
Amiga/CS80 or CBM "DOS" at the firmware level, and a generic "IEEE
Disk" would be useful in a number of environments, not just HP and
CBM. I wouldn't require that the same box be able to do either
Amiga/CS80 and CBM DOS without a reflash, but it might not be
impossible if the MCU has enough code space and perhaps a spare I/O
bit to look for a configuration jumper (or even some sort of "magic"
secondary address to send configuration requests to).
There are several options in the PET/CBM/C64 arena for IEC (serialized
IEEE), but so far, I don't know that any of the discussions or
proposed projects for a parallel IEEE disk have progressed to the
point of hardware you can build and firmware you can download.
I've been tinkering with this idea for quite some time and have a couple of
observations.
The project I'm been pondering would use AVR micro along with an IDE disk to
emulate a CS80 drive. The IDE interface is pretty simple although like the
HPIB it does requires a lot of I/O lines. Between all the handshaking and
control signals with the IDE and HPIB devices, it would require a TON of
I/O. Either that or you have to do some fancy muxing of the I/O.
So, to make the HPIB control simpler, I'd prefer to use a HPIB controller
chip like the NEC7210. That chip just hangs on an 8-bit bus and uses
internal registers to free up some of the I/O lines on the micro. The
biggest problem is finding a reliable supply of HPIB controller chips.
My solution to this would be to break this project in to two separate
smaller projects. Firstly, use a separate microprocessor to emulate the 7210
controller chip. This would provide several advantages:
1.) You wouldn't need to worry about the supply of 7210's for future
projects. Simply burn a $4 AVR and you have a HPIB controller chip.
2.) The dedicated controller would handle all the low-level interface stuff,
the signaling, BUS timing, etc... So, programming would be much simpler. You
just read and write to the AVR controller "registers" just like you would a
7210.
3.) The 75160/1 pairs are still available. I think DIGIKEY has them in stock
at a reasonable price. Note that these are not "just" I/O buffers. There are
a few additional gates in the devices that add some more logic that one
might expect.
So, the AVR could eliminate the need for the 75160/1 bus driver chips. If
you fry a $4 AVR... Who cares? It doesn't cost much more than the dedicated
drivers.
Hmmm... The more I think about this, the less certain I am about eliminating
the 75160/1 pairs. Normally, one would know what direction data was moving
on a bus. But with HPIB, it can be ambigious.
IE: A device might assert a SRQ (service request) at the same time another
device is receiving data. So... What direction is the data moving on the
bus. The talker is asserting some of the control lines, the listener is
asserting some of the lines (NFRD, etc), and a third device might be
asserting some lines. Hmmm. I gotta give this a little more thought.
4.) You might be able to build a simple "adapter" board and use the AVR in
place of hard-to-find 7210's in existing equipment.
5.) Modifying the project for other purposes would be much easier. For
instance, you could use the same project with some code modifications to
emulate a HPIB tape drive, a HPIB instrument, a bus analyzer, etc...
Just a few quick observations.
See yas, SteveRob
