23 Oct
2005
23 Oct
'05
9:48 a.m.
On Saturday 22 October 2005 11:37 pm, cctalk-request at classiccmp.org wrote:
From: msokolov at ivan.Harhan.ORG (Michael Sokolov)
Subject: FPGA VAX update
To: cctalk at classiccmp.org
Message-ID: <0510230037.AA21104 at ivan.Harhan.ORG>
Hello fellow ClassicCmp'ers,
Stuff deleted -
I'll be using Icarus to compile Verilog to EDIF. I
have heard sermons
from "paid professional" chip designers working on the dark side (making
non-free designs with non-free tools) about how inferior it is compared
to whatever non-free shit they use, but I don't care, freedom is more
important to me than quality. (And I mean free as in speech, not as in
beer.)
Michael,
First of all - I love Icarus (I must - I organized and wrote the test suite
for it ;-) and I use it for module level stuff at home before I import to the
professional tools BUT there is another option for simulation.
There is a program called Veritakwin running on Windows that is $50 and is
many times faster (4-5X) than Icarus. It is a windowed environment and has a
built in wave-form viewer. Think Mentor modelsim like. You might think about
it as a verilog too. The implementation is more complete than Icarus and also
faster.
The problem is of course with place & route and the
actual FPGA bitstream
or SOF (SRAM object file) generation. The first part of the problem is
that the fucking FPGA vendors won't give us a complete description of
the FPGA routing fabric and bitstream/SOF format. The second part of
the problem is that even if this information were pried out or reverse-
engineered, someone would still have to write an open source P&R tool,
which is a *major* task - certainly not for me, designing a VAX CPU is
enough work for me, I don't need the extra task of developing an FPGA
P&R tool.
There are only two practical choices when it comes to the actual target
FPGA: A or X, which of course stand for Altera and Xilinx. I would be
content with either if I could work out a usable toolchain for it that
would take me from EDIF (Icarus Verilog output) to the SOF or bitstream
file (A/X respective terminology).
To make the long story short, there are two specific areas where I could
use help from other listmembers:
1. The Xilinx option. The maintainer of Icarus Verilog
only has
experience with Xilinx. He uses X's proprietary P&R tools, but they are
command line tools and are available for Solaris and Linux in addition
to Losedows. (I still can't figure out whether the Xilinx-blessed Linux
version is truly native or runs through WINE.) Icarus documentation
includes a complete worked-out example of a build starting from Verilog
and ending in a bitstream, feeding iverilog output (EDIF) to the command
line tools from X's proprietary software.
First - Steve Williams uses this path on a daily basis for his day job, so it
is a proven path.
Second - the Xilinx tool is running native on Linux but is a bit flakey for
6.0.
What I don't understand is - Why not use the Synthesis tool in Webpack as
well? Why even BOTHER with Icarus for this part of the tool chain? It isn't
as good as Synplify - but it DOES work most of the time??????
Since this might be a workable option for me, does
anyone here have the
Xilinx Foundation tools installed on a Solaris or Linux box on which I
could get an account for work on my FPGA VAX project?
The Windows version is faster than the Solaris version. I believe the lInux
version is faster than either...though that is from a very faulty memory.
If I were setting up for a private (home) project with FPGAs today I would
choose Veritakwin and Webpack as my tool chain. I get MUCH faster
simulations, and a working synthesis/P&R tool in Webpack. (I've really never
figured out why Steve bothered to do the Synthesis tool beyond the challenge
of it...maybe that's the answer..)
Good luck with your project.
Steve Wilson (Professional Verilog slinger)