Fwd: Completed Floppy Disk Controller Design

Status: RO Sender: fufu-l(a)telia.com Reply-To: fufu-l(a)telia.com Date: Mon, 14 May 2001 08:47:25 -0700 From: "Michael Holley" <holley(a)mail.hyperlynx.com> To: Multiple recipients of fufu-l <fufu-l(a)telia.com> Subject: Completed Floppy Disk Controller Design I have finished the design of a new floppy disk controller for the S30 I/O bus. The card emulates the SWTPC DC-4 with a few additions. The design uses a Western Digital WD2797 FDC that supports double density format. The WD2797 is a superset of the WD1797 and WD1691 and is software compatible. The card will fit in an old 6800-style case or the newer 6809-style case with the connectors coming out the back. The clock frequency is programmable so the card should work with 3.5-inch drives. The design is complete but needs to be reviewed.(There are errors and omissions.) After a few weeks of review I will have 2 (or 4) boards made. I am looking for someone who has a system with SS30 I/O bus to help debug the board. After the design is tested I will order 10 or so boards with silk-screen and solder mask. The design documents can be found at: http://members.aol.com/swtpc6800/FDC2/FDC_Index.htm I still have some design documents in process and will add them when they are done. The difficulty I was having with a discrete logic design was board layout. I was going to use some 20-pin programmable logic devices such as the 16V8 but programming them is difficult. (I have an old Data I/O Model 29 programmer but I haven't turned it on in 10 years.) I was looking for an in-circuit programmable device. I decided to use the Xilinx XC9500 CPLD family. They are low cost ($6), the development software is free, and the programming hardware is simple. Another reason is that I have worked with these devices since they were developed by Plus Logic in the late 1980s. Somewhere I have a Plus Logic 2020 engineering sample. The development software is based on the ABEL and Synario software that I developed at Data I/O. I chose the XC9572, which has 72 Macrocells and comes in an 84-pin PLCC package. This device holds all of the discrete logic devices needed in the design. The timer IC and one-shot IC are external along with the buffers. I could have connected the disk drive directly to the CPLD but I felt the low cost buffers would be easier to replace in the future. The device is re-programmable so design changes are easy. I am only using about half of the device now. For the PCB layout I went with ExpressPCB because they have free software and they do low cost double-sided boards. A friend of mine has had good luck with them. I have access to very high-end PCB layout software at work but I want the design to be public domain. (If I published the design files in PADS format you would have to buy a $10,000 PADS PowerPCB software package to modify them.) After the layout is done I will publish the PBC file. If someone wants to review the current design I can email you the file. The only rare part in the design is the WD2797; I bought 10 of them from BG Micro before I started the design. The rest of the parts are available from Digi-Key with exception of a few ICs that I found at Jameco. The complete kit of parts cost $50 plus about $40 for the circuit board. I am going to acquire enough parts to build 10 boards. I still need to write the calibration procedure and add the required test point to the board. I just noticed a trace clearance problem near pin one of the 34-pin connectors. The DDEN line is controlled by the CPLD so we can add the logic for MS-DOS floppies. This logic in not in the CPLD yet. ----------------------------------------------- Michael Holley holley(a)hyperlynx.com Innoveda Phone: (425) 869-2320 Fax: (425) 881-1008 Direct Line (425) 497-5075 ----------------------------------------------- -- FLEX & UniFLEX Users' mailing List http://www.flexusergroup.com/ http://w1.503.telia.com/~u50302970/