The driver is
generally the easy part; there are quite a few FETs
out there that ought to do the job acceptably. You need a total
(driver + receiver) capacitance of 9.35 pf, which is generally
the tallest order, but it's easy enough to limit the slew rate of
the pulldown by putting a series resistor in line with the gate.
I believe Peter Wallace recommended the FDV301N, which seems as
good as any; put one for the driver and one at the source as a
gate for a group of them, and you should have a pretty effective
transceiver. It might take a bit of space, and you'll eat a lot
in assembly if you're not doing it yourself, but as Dave McGuire
pointed out, if your main logic is contained in a micro and/or
CPLD/FPGA, you're going to have plenty of space. And for SOT-23
packages, you can probably get close enough to the density of the
original (quad-gate) DIP devices. The FDV301N claims a Coss of
6 pf, though I haven't done my homework to think about how the
other parasitics affect the input capacitance.
I've been thinking about this too. My thought was to use a 74abt125 as the driver.
Since it's a tri-state output, I'd ground the input and use the OE enable as the
data (which would
invert it). IOL is 64ma. Rise/fall times are 10ns/V but that could be slowed with a
series
resistor.
Thoughts?
Is there a speed penalty for using /OE instead of the gate's actual input?
-Dave
--
Dave McGuire, AK4HZ
New Kensington, PA