AED/DMA - Re: DOOM

14 Jan 2013

...
   [...]; the DMA
transfer rate may not be the limiting factor.  You'd have to halve the rate in
any case since the CPU would take an
 equal amount of time doing memory cycles to update it? 
Maybe.  Depends on what limits "the DMA transfer rate".  In general,
it's possible, depending on the memory subsystem, that DMA out of
memory does not interfere with CPU access to memory unless they are
accessing locations too close to one another (eg, the same 32-bit line
of memory).  Also possible is that the memory bus is enough faster than
both the DMA path and the CPU path that, while they can collide over
it, it can sustain both data streams at once without trouble.

I don't know enough of PDP-11 memory subsystems to know whether either
of those is true of any of them, though.

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AED/DMA - Re: DOOM