22 Jul
2018
22 Jul
'18
11:07 a.m.
From: Paul Birkel
Unfortunately there's not much documentation for
the MS11.
??? We're actually pretty well off, there; we have:
- MS11 Maintenance Manual (DEC-11-HMSAA-D-D)
- MS11 MOS Memory Troubleshooting Guide (DEC-11-HMSTS-A-D)
- MS11-B Engineering Drawings
About all we're missing are the MS11-A/C data board engineering drawings.
(The control board is in the MS11-B prints.)
From: Mattis Lind
This could mean that 16 bit data is in the L chips
while the faster
chips are used for a 10 bit cache tag.
Sounds plausible.
And of course those two I/O connectors don't
belong on a cache.
...
Those IO connectors are connected to two double height boards in 26 /27
AB. They are also made by ACT and contain a few TTL chips.
If the board is a cache, how does it get filled? It would have to listen to
the UNIBUS the memory is on. So I'm guessing that's that those connectors and
boards are for.
Note that there has to be a signal from FastBus (anyone know the correct
capitalization for that?) which tells the CPU if the MS11 has a given address
or not (given the way the MS11 can be configured as to size and address), so
the cache board could use that line to tell the CPU whether or not the
location in question is in the cache.
Noel