3 Nov
2001
3 Nov
'01
5:45 a.m.
see below, plz.
Dick
----- Original Message -----
From: "Ben Franchuk" <bfranchuk(a)jetnet.ab.ca
To: <classiccmp(a)classiccmp.org
Sent: Saturday, November 03, 2001 9:23 AM
Subject: Re: CPU design at the gate level
Chuck McManis wrote:
The random logic fits better in the CPLDs than in FPGA's, since the routing
doesn't get as tangled as the device fills up. I don't like the way the XILINX
software deals with CPLD's as opposed to FPGA's, though. It's bad there, but
the ALTERA software has really given me cause to wonder. A part of the problem
is that the software doesn't try to squeeze all it can out of the available
resources. Consequently, any effort at approaching full utilization of
available resources has to be done by hand, which is very time-consuming
therefore costly.
Which sorts of logic are more difficult to implement depends to large extent on
the device architecture. One immediately has to draw a distinction between the
CPLD and the FPGA. The former makes it easy to use the available resources,
though not necessarily "fully" utilize them, while the FPGA simply gives you
more, though it's unlikely you'll approach the level of utilization of possible
with a CPLD. The CPLD has more multiplexing/gating/routing resources per
register than the FPGA, and its timing is generally quite deterministic, while
the FPGA has vastly more register resources, but makes you pay for using them by
consuming lots of routing resources and CLB's for the gating, say, in a big
synchronous counter. That also reduces the overall performance of the counter,
since the routing delays are cumulative. What's more, the timing is impacted by
when the routing software encounters a given construct, hence, a counter that
runs easily at 120 MHz in one design may turn out to run no faster than 80 in
another, all that in a device that is advertised suitable for 250 MHz operation.
The above statement is completely untrue. You can
get 10 - 100x the "ttl"
equivalent logic in a 44 pin PLCC. Check out the XC9572 some time,
depending on your logic you can replace a whole bunch of TTL and they are
$5.53 each from Digikey, quantity 1. Or go to 84 pin PLCC, still allows you
to do through hole work for $7.00 and get 50% more gates.
That is true but random logic is hard to judge how much will fit in a
FPGA. Normal glue logic often fits well as well as simple I/O devices
like a printer port. It is random state logic, Alu's and memory devices
that don't fit well and that is often what is needed.
Note you can still find the old TTL but you pay a arm and a leg for
them.
A 74LS181 that was $1 in Jameco is now $4 here. A 74LS382 is $8.00.
If you need old replacement parts this looks to be the spot.
http://www.rocelec.com/
Note the 74182 is the carry lookahead.
<snip Makes for a mighty thin RACK mount.:)
I've got a 256Kx16 DRAM chip lying on the desk right now. They're not
that
uncommon, but they're not a popular chip in the PC market any longer, since the
evolution of AGP. They were common on VLB and PCI SVGA cards. That would have
made the jaws drop back in the days when folks actually used PDP11/70's.