Vincent Slyngstad wrote:
From: "Don North" <ak6dn at
mindspring.com>
Using all these pieces I was able to implement a
PDP-8e (no EAE, at
least yet)
that passes all the basic CPU diagnostics. Cast in hardware on the
digilent
Pegasus it occupies about 13% of an XC2S200-6, and runs at 15ns per
clock tick
(4 ticks per cycle), which is about 20X faster than a real PDP-8m
(1200ns/60ns).
The base CPU is about 500 lines of verilog.
One of the questions I have kicking around (I even bought an XESS
board) was: How hard would it be to get a PDP-8 core into an FPGA
and arrange the pinout to correspond to the 6100 or 6120?
Then it wouldn't be necessary to desolder 6120's from Decmates to
get our SBC6120's working :-).
Getting the logical signals to match would not
be that big a deal; the
larger
problem would be getting a compatible form factor. I retargeted my PDP8
above
to a XC2S30 and it occupies about 75% of the device. In a CS144 (small 0.8mm
pitch BGA) one could probably make a DIP40 plugin carrier that was pin
compatible
to either the 6100 or 6120 parts.
Signal level compatibility (ie, 5V tolerance) and power supply compatibility
(5V/3.3V/2.5V/1.8V) would be more difficult problems. Some of the older
FPGAs
offer 5V tolerant I/Os (ie, Spartan2) but the newer ones (IIe, Spartan3)
do not.
None of these devices use 5V supplies, they are all 1.8V~3.3V at most.
The power
supply issue can be solved by a small linear regulator, but I/O level
compatibility
is a stickier problem.
Anyway, it is an interesting problem, probably solvable given more
thought and
research. However, I suspect any low volume solution will still be more
costly
than just tracking down old IM6100 ICs for $10-$20. Not nearly as much
fun, tho.
Don