CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

One has to realize that all complex chips are done in Verilog or VHDL. Many old designs in processors can be re-implemented from timing and bus diagrams. This is no longer possible with todays processors like Intel or AMD processors. The complexity of possible sequential events are more than is practical to try to analyze from the pins. One can implement an instruction set but you'll never get close to the bus activity of current processors. I would say that the most important part of either language is the ability to describe the time of simultaneous events. This is unlike most programs written in C or such. Of course, one can write a simulation language in C. Dwight ________________________________ From: cctalk <cctalk-bounces at classiccmp.org> on behalf of Chuck Guzis <cclist at sydex.com> Sent: Tuesday, June 21, 2016 8:24:44 AM To: General Discussion: On-Topic and Off-Topic Posts Subject: Re: CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs? On 06/21/2016 07:25 AM, Paul Koning wrote: I take it that your PPs use the "one ALU, ten memories" model of the 6600 and not the independent PPUs of the 7600 and 180? Will your 6600 have an option for ECS? --Chuck