21 Mar
2001
21 Mar
'01
6:34 p.m.
VIC-II and SID are perpetually problematic, especially
SID since it's part
analogue (and probably so is VIC, for that matter). The timings are well known
but the interactions between registers are sometimes unpredictable (but rest
assured out there is a game that depends on that particular interaction).
Emulator writers have torn their hair out for years thanks to Commodore's
loose hardware design philosophy.
You would need a very large and complex FPGA to fully emulate the range of
behaviours these remarkable (and bizarre) chips demonstrate.
Hmm, analogue. I hadn't thought of that. But I thought the chips had been
pretty well reverse-engineered by now.
Does anyone know of gate-level (or similar) diagrams for the chips? We now
have the gate-level diagrams for the Atari custom chips, thanks to Curt
Vendel, so this is the chance for you Commodore fans to prove your inherent
superiority! :)
-- Derek