CPU design at the gate level

While it makes sense that clock distribution would increase power consumption, I don't think that synchronous/vs asynchronous design is the point of the article to which you refer. Synchronous designs do, however, require that every stage of the "pipeline" is clocked from the same clock, there are ways of synchonizing events between asynchronous modules in a circuit that minimize the risks of metastability, and that's the principal bugaboo that gave rise to the popularity of all-synchronous design. Moreover, it requires somewhat more imagination and resourcefulness to design efficiently interacting asynchronous circuits, which tend, generally to be a mite thriftier if implemented in discrete components, yet yield little benefit to the designer of CPLD/FPGA-based logic. The type of CPU they're referring to in this case, methinks, is a level-latched rather than edge-triggered-flip-flop based architecture. It has some potential, but, since it's not the cookbook sort of structure that is taught in colleges these days, it will be a while before it's fully explored. The MOT 6800 and MOS-Technology 650x types used that sort of approach, using the "clock" to gate and steer rather than to trigger events. Dick ----- Original Message ----- From: "Derek Peschel" <dpeschel(a)eskimo.com> To: <classiccmp(a)classiccmp.org> Sent: Saturday, September 22, 2001 1:40 PM Subject: Re: CPU design at the gate level became '80's.