11 Apr
2017
11 Apr
'17
6:05 p.m.
On 04/11/2017 04:53 PM, Jecel Assumpcao Jr. via cctalk wrote:
I consider the heart of any modern high performance
CPU to be a
dataflow architecture (described as an "out of order execution
engine") with a hardware to translate the macrocode (CISC or RISC) to
the dataflow graph and tokens on the fly.
I wouldn't characterize an
out-of-order execution scheduler as
"dataflow", at least not in the traditional sense.
Certainly, nobody that I was aware of ever categorized, say, a CDC 6600
as a dataflow machine.
At least not in the same sense that I'd categorize a NEC uPD7281 as a
dataflow device.
--Chuck