OT: DRAM memory controllers within FPGAs

On 26/01/11 20:29, Keith M wrote: You're using an Altera/Terasic DE1 (Cyclone II Starter Kit) developer board, aren't you? Sometimes it's less effort to write code from scratch than to try and make someone else's code work... Oh, the Milkymist SDRAM controller core... That should work quite nicely. Sebastien Bordeauducq is a frickin' good HDL coder... I didn't use it because I wanted something with a WISHBONE interface, and there was a (remote) possibility that my project (at the time) might end up as a commercial product. Hence, introducing GPL code into the HDL would be a Really Bad Idea. You could have an SRAM-like interface, you'd just need to have a BUSY or DTACK output to go with it. Is that close enough? Either way, you're not getting rid of the BUSY output... Almost all SDRAM chips can handle page reads. Basically, you pick a row, then read a full page of data out (usually 8 words or so). You could buffer that in a dual-port RAM. It'll speed up sequential memory access, at the cost of slowing down random access. It also falls into the categories "a bit of a pig to implement" and "can't quite get my head around the logic", which is why it's still on my to-do list! Also, I haven't needed it -- the LM32 DCACHE and ICACHE work well enough for my requirements. -- Phil. classiccmp at philpem.me.uk http://www.philpem.me.uk/