30 Oct
2010
30 Oct
'10
12:29 p.m.
On 10/30/10 2:35 PM, Philip Pemberton wrote:
I can't see any real reason why SA1000 support
couldn't be added to the
bridge-board. Looks like the only changes required would be:
- An oscillator to generate the 3.6866us +/- 0.1% timing clock (270982
to 271524Hz, nominal 271253Hz). Although I have no idea what standard
crystal frequencies could be used to generate that signal. The FPGA's
PLL might be persuaded to do it, though, I'll have to check.
You could stick a little AD9833 (or similar) DDS chip on there. It's
overkill, but they're pretty cheap now, and you'll get the desired
frequency spot-on.
-Dave
--
Dave McGuire
Port Charlotte, FL