On 22.12.2013 17:43, Al Kossow wrote:
Here is a first draft. Anything wrong/missing
architecturally?
Can't resist to comment on this ... :-)
Does any driver watch the value of ADR,WC
in memory while a DMA is occurring?
Good question. But if it is visible - it should
be visible.
It should be possible to simulate all the front panel
functions of
an Omnibus machine and to capture all of the state in real time for
all of the major registers from watching Omnibus transactions.
I once
"tried" to count the amount of bus drivers and receivers to cover *ALL*
on the Omnibus. Lots of signals. But having an FPGA with full access would be
quite handy.
All registers and supported peripherals are obviously
soft. The configuration
is stored on the SD, along with the FPGA bitstream. Everything should be
reconfigurable through transactions across the Ethernet by updating files on
the SD card.
Hm.... This is where I don't like the approach: I'd prefer
having an MII or GMII
interface on the FPGA. And I'd think of using a larger FPGA instead of an
external ARM SoC.
The coolest way would probably be an onboard ethernet switch, external ARM with
ethernet, a CPLD that glues the ARM's memory interface to the FPGA and FPGA
configuration logic. With such a setup you could to just everything.
I'm not sure if a local serial interface would be
that useful other than
for debugging messages.
For the Linux console on the ARM, of course - which is
debugging :-)
:-)