16 Jul
2007
16 Jul
'07
10:31 a.m.
Chuck Guzis wrote:
Carrying this idea of old logic families to its next
stage, I wonder
if it would still be possible to get some "hard" ferrite toroids to
implement a digital clock design in core logic? I'm not up to snuff
on what's available in the small-quantity market.
Sometimes it's fun just to go through the design exercise. An initial thought
was that, either:
- you'd need a "non-core" latch to hold the state of the core counter
logic
before driving the Nixies because you don't get a static state level out of
the cores, at which point you have as much complexity of non-core logic as you
would without using the cores;
- or, come up with a scheme where you're reading and refreshing the cores at
a high enough rate to drive the Nixies in pulse mode, but while retaining the
counter state. It would be neat if you could get enough pulse energy out of
the cores to drive the Nixies without intervening transistors.
I'd still like to read that document you pointed to about the SS90 containing the
core logic principles but I think it's about 20-30 MB and have yet to download
it.