On Jan 2, 2014, at 11:15 AM, Peter Corlett <abuse at cabal.org.uk> wrote:
On Sun, Dec 29, 2013 at 11:05:35AM -0800, Al Kossow
wrote:
[...]
I had been tinkering with Cyclone parts, but most
people here use Xilinx. I
think Verilog vs VHDL is about half and half. Over Christmas, I bought myself
a Pipistrello board with level converter shield
http://pipistrello.saanlima.com/index.php?title=Welcome_to_Pipistrello
My research into FPGAs so far has come up with the following:
I am informed that Xilinx's FPGAs are better than Altera's, but Altera's
development tools are much better. Having actually *used* Altera's Quartus II
and found it to be pretty hateful, I dread to think how horrible Xilinx's tools
must be.
Verilog claims to be C-like, but this isn't particularly true. Some of its
expression syntax is C-inspired, but you could describe it as Perl-like or
Java-like at that point! It's somewhat more Perl-like in that you can just glue
fragments together and it'll generally work. Even a rank amateur like myself
managed to get a blinking LED after barely twenty hours or so of effort :)
I don?t know Verilog, but if it really is PERL-like that?s quite a strong condemnation.
VHDL appears to be much more strongly-typed, which I approve of as it means
code that actually compiles is much more likely to be correct, however a
beginner is going to find themselves utterly flummoxed because they're having
to learn circuit design and a rather picky language. I decided to leave
learning VHDL for the day when I embark upon a more ambitious project that
would benefit from a more rigorous design.
VHDL is clearly inspired by Ada. I?ve done some elementary VHDL work and like it a lot.
FWIW, there is an open source VHDL simulator available (just a simulator, not tied to any
real world FPGA) that?s integrated into GCC ? called GHDL. It seems to work well; I?ve
fed it some rather large models that simulate nicely.
No matter the syntax, an HDL is a very different beast than a programming languages.
Programs are single threads of execution, give or take some threading stuff thrown on top.
FPGA designs inherently do many things in parallel. Languages like VHDL make that
explicit, and you do need to understand this for your design to make any sense. When I
mentioned the Forth chip design whose designer didn?t realize VHDL isn?t C, that?s what I
meant ? not the differences in syntax, which are trivial enough to handle, but the
fundamental difference in conceptual model. If you don?t know that changes to a VHDL
?signal? are not visible until the next model cycle, you won?t get very far...
paul