19 Sep
2001
19 Sep
'01
2:14 a.m.
-----Original Message-----
[mailto:owner-classiccmp@classiccmp.org]On Behalf Of emanuel stiebler
Jonathan Engdahl wrote:
...
The idea is to write PDP-11 microcode for the PC platform,
rather running an
"emulator" under Windows or whatever.
The Pentium would be viewed as the
micro-architecture, the PDP-11 as the real machine. It would be
table driven
> and fully expanded, using the PC memory rather extravagantly.
OK. But, this microcode has to have an OS around. because:
- how to use the MMU ?
- you need access to serial ports ?
- disks
- tapes
- ethernet
- etc.
Or do you like to program this stuff all by yourself ?
Still, definitely not a Windoze, but somekind of ukernel.
Anyway, start with it, and we see one day ;-)
No OS, not at all.
The x86 MMU is just part of the microengine used to implement the MMU of the
target machine. View it as part of the hardware-assist, just like the opcode
mapping ROMs of traditional microcoded machines. On a micro coded machine,
typically the last opcode of the emulation of any particular macro-opcode is
a fetch and dispatch of the next opcode. This jams a new address into the
micro-PC to get you to the appropriate routine to emulate the new opcode.
Interrupts are handled similarly -- if the interrupt flag is set, it
overrides the opcode dispatch and puts you at a routine to take care of
emulating an interrupt. So using a trap generating hardware assist in
microcode is nothing new.
I/O registers are implemented by trapping to a hardware emulation routine
when the CPU microcode writes to the I/O register. The I/O page is set up in
the x86 MMU as protected. Say you do a "mov r0,@$177560" (that's the
console
data port, right?) The microcode for this is something like:
LODSW ; SI is R7, fetch second word of opcode to AX
MOV [DSPACE+AX},BX ; say BX is R0, save R0 to EA in dspace
CMP BX,#0 ; set condition codes
LODSW ; fetch next opcode
JMP [DISPATCH+AX*4] ; dispatch next opcode
(I'm not too sure of the x86 addressing modes, it's so unorthogonal, so
don't criticize my assembly code).
However when you do this, the x86 MMU says "nothing doing" and traps you to
the illegal access routine. This routine will look at the effective address
that caused the violation, and will dispatch you to a routine that emulates
the SLU. This routine will grab the data that was going to be written, and
write it instead to the RXDATA port of COM1:. The trap routine will then
return (without restarting the MOV [DSPACE+AX},BX opcode). Any other
hardware can be emulated in a similar fashion. Wherever possible, let the
real hardware do the work, all the trap routines have to do is reroute the
data to the right places.
No OS, no microkernel, except a couple routines to setup the MMU, and to
handle dispatching traps. I realize that programming the x86 MMU by hand
will be nasty. I've done it once before, and gave up after a while, but I
did get it to work a little. Maybe I can steal some code from the Linux
kernel.
--
Jonathan Engdahl???????????????? Rockwell Automation
Principal Research Engineer????? 24800 Tungsten Road
Advanced Technology????????????? Euclid, OH 44117, USA
Euclid Labs????????????????????? engdahl(a)cle.ab.com 216-266-6409