20 Nov
2017
20 Nov
'17
4:49 a.m.
On 11/19/2017 10:51 PM, Eric Smith wrote:
On Nov 19, 2017 7:18 PM, "allison via
cctalk" <cctalk at classiccmp.org
<mailto:cctalk at classiccmp.org>> wrote:
The rest is the specific implementation.? What happens if the CPU is
1802 or something else that does not match the 6500 or 8080z80 models.
There is nothing that prevents either the serial or parallel
arbitration schemes from working with other processors.
Understood but not always easily applied.
In the case of the 1802, it would work easily for
interrupts, but
would need some additional circuitry for DMA, because the 1802 doesn't
include any feature whereby another bus master can request that the
1802 surrender control of the bus. Instead, the 1802 has a built-in
single-channel DMA controller.
Its why I picked that one.
That 1802 bus master problem exists for interfacing
_any_ sort of bus
master to any 1802, and is totally independent of what kind of DMA
arbitration is chosen.
True, but as a potential candidate on a generalized bus how do you
handle that, besides wait states
or processor clock stall? Of course being CMOS its easily done at a cost
of performance.
All of this is targeting a generalized bus to run a large selection of
cpus possibly mixed with radically different bus cycles.
Allison