29 Apr
2013
29 Apr
'13
7:36 a.m.
On 4/28/2013 2:34 PM, Andy Holt wrote:
While on the subject of Atlas and referencing another
thread on this list it
would be a /real/ challenge to implement on an FPGA -
Not for the lack of circuit diagrams (I understand several copies still
exist)
Not for the use of "wired-or" (don't know if Atlas used this logic
technique, but several later Ferranti machines did)
But because it used asynchronous logic which is contrary to the design
philosophy of FPGAs (and almost all other modern logic for that matter)
It justs fucks up the timing routines. I have allways thought the async
logic requires glitch free gates, and that may be a problem.
Andy
Ben.