Hi, I did post my solution to the group but it does not seem to have got
there, I have noterd that sometimes my mails dont get through so here it is
again.
Dave H
Hi
The problem is with the gating of the IOT ( 6RK4L) before its applied to
the 74161 as CLK (2),
on drawing M7105-0-1 REV B , MAJOR REGISTERS (D06)
this is done by E47 , E41 and E28, the problen is that they are taking the
6RK4, the IOT, and trying to truncate it with a modified TP3, and if this
TP3 timeing is a little off then you get a spike at the trailing edge.
Different revisions of this board seem to have different ways of generating
this TP3, and mine has a wire patch in place .
Have a look at E18(2), the CLK while doing an DLCA scope loop and see what
you get.
My fix was as follows, "piggy back" a 7474 onto E41, just the gnd and
power , 7 and 14, bend the rest of the pins away.
On the 7474 connect both the D(2) and the CLR (1) to E41(10), then connect
the CK(3) to E41(9).
Cut the track from E41(8) to E28(12). Connect fron the 7474 op(5) to
E28(12).
The result of this is to latch the TP3 pulse so it cant go low before the
end of the IOT.
This shoul be it, I had to decifer my notes and look at the board so I hope
iv got it right!
Lets hope this is your problem, the RK8E sure is fun to work with , I had to
change several IC's to get my set working at all.
Cheers
Dave
----- Original Message -----
From: "Al Kossow" <aek at bitsavers.org>
To: <cctalk at classiccmp.org>
Sent: Monday, March 03, 2014 5:51 PM
Subject: Re: PDP 8/e, RK8E Weirdness - Scope Traces - Update
On 3/3/14 8:37 AM, Rick Bensene wrote:
If anyone wants the procedure for the
modification, I can Email it to
you. Just drop me an Email and I'll send it along.
Please just post it to the list so that is it archived.
-----
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