25 Apr
2016
25 Apr
'16
8:37 a.m.
On Mon, 25 Apr 2016, Paul Koning wrote:
I know some very ancient MIPS processors had oddball
required delays
("load delay"?) that went away after. And there's the misbegotten
"branch delay slot" -- but that is part of the architecture and applies
to all MIPS even long after the reason for it was ancient history.
See my other posting in this thread for details.
NB branch delay slots have been gradually disappearing too as the
architecture evolved. Branches with no delay slot (compact branches)
first appeared with the MIPS16 ISA back in ~1996, then compact jumps were
added with the MIPS16e ISA extension. Later on compact branches and jumps
reappeared in the microMIPS ISA (assembly source level compatible with the
regular MIPS ISA).
With the recent R6 architecture revision compact branches and jumps were
added to the regular ISA and delay slots removed altogether from the
microMIPS ISA (R6 breaks full backwards compatibility for pipeline
performance reasons; some old inventions were deemed too costly in terms
of die space and power consumption for a contemporary architecture in
embedded use).
This is drifting away from the scope of our mailing list though.
FWIW,
Maciej