IOB6120 Anyone?

I have recently completed testing of some IOB6120 boards, and I've sold a few in the Spare Time Gizmos group, but now I'm offering them for sale here, too. This isn't related to the earlier group buy (which, as far as I know, folks are still waiting for), and in fact isn't a group buy at all. I've already bought the necessary materials, assembled, and even tested these things. (I have no bare boards or unassembled kits available.) According to my email archive, $215 was the asking price for similarly configured boards back when, and that still seems reasonable to me. A little more for international shipping. (Feel free to donate additional funds, of course :-).) There are some minor variations between the units -- most have box headers for the (untested) digital I/O interface option, but a couple have bare male headers. All have box headers for the serial ports, and on the bottom all have a bare 50 pin male header, a two-pin female header (for CPREQ), and a bit of purple electrical tape to protect the +3V poles of the batteries 63-37 tin-lead solder (and will still have residual flux on them). If you want one of these, please contact me off-list: v.slyngstad at frontier.com. Here are the particulars of the testing I have done: Each of the four ram-disk has passed the "RF" pattern test. The CF interface has performed a "DF" command on even and odd numbered partitions, and booted OS/8 successfully from a bootable CF. The flash responds to commands and has been programmed. It should be noted that these boards have 29F400 flash instead of 28F400 flash installed. This means you'd need to get new firmware for the IOB6120 to be able to reprogram the flash with the "FL" command. I can probably provide a pair of 27256 EPROM programmed with unofficial firmware for about an additional $10 , but I have only so many chips, and would rather not unless you actually plan to modify the flash. The FLASH extension ROM is recognized and correctly initializes the FPGA, which then passes the self-tests. The clock/calendar has been set (PDT) and keeps the date/time and partition map settings for days at a time, so the battery and battery back-up seem to be working. The VT52 terminal emulation has been tried and works. Right-CTL-G generates a "beep" from the speaker as expected. The 3 serial ports all independently display characters and accept input at 9600 baud. I am prepared to throw in a single serial cable -- with a 10 pin header on one end, and a male DE9 connector on the other. The printer port is capable of individually lighting LEDs from each of the 7 data pins. (Data pin 8 is actually masked off in the FPGA, so it's obviously set up for 7-bit ASCII.) (I don't have a proper working parallel printer to hook up for actual printing.) Vince -- o< The ASCII Ribbon Campaign Against HTML Email!