15 Jul
2015
15 Jul
'15
10:54 a.m.
I suggest that this is really somewhere in between, but MUCH closer to
the "original design" than to "if you design a circuit for an FPGA".
After all, in an FPGA, the original SMS cards from the IBM 1400/7000
series would not be present - so in that sense, nothing is really taking
the original design - at the transistor/component level.
But I submit that making a set of rule-based changes to the original
design so that it will function in an FPGA really is capturing that
existing design. (And nobody but you added the "schematic capture" part
of it - that is not, nor has never been, my plan).
The result should capture something pretty darn close to how the
original actually operated, which is the idea.
And, as far as that goes, the VHDL or Verilog version has not, in my
experience, required those modifications. The modifications had to be
put in to ensure that the synthesis step produced something that has a
chance of actually running.
JRJ
On 7/15/2015 12:21 AM, tony duell wrote:
That is not 'taking an existing design and feeding it into a schematic capture
program'. It's modifying the
design (adding the D-types to synchronise signals and removed glitches). I do not dispute
you can do that.
-tony
My
experience of FPGAs is that if you design a circuit for an FPGA it will work. If you take
an existing design
feed it into a schematic capture program and compile it for an FPGA then it won't.
Actually, you can, and I have done so - provided that the original
machine was slow enough. It works, in part, because the FPGA's are
sooooooooooo much faster than the original design, that you can use the
"trailing D flip flop" approach I described to convert the former into
the latter - the glitches occur on the time scale of the FPGA logic, but
are gone by the time the next simulated machine clock arrives.