29 Apr
2013
29 Apr
'13
9:02 a.m.
On Apr 29, 2013, at 11:59 AM, David Riley <fraveydank at gmail.com> wrote:
Yes, the static timing analyzers are really built for
synchronous
designs. You can do asynchronous logic with glitches, but you
then have to carry a strobe with you, which almost defeats the
point. There's an FPGA company called Achronix whose first FPGA
offerings claimed to be reaping the benefits of clockless logic,
but I don't see that anywhere in their literature now (their name
still belies their origins, though).
Whoops, spoke too soon. They're still talking about it.
http://www.achronix.com/technology/picopipe.html
Wonder how well it integrates with traditional HDLs. I've never
actually worked with Achronix devices, but they certainly seem to
occupy the high end and have things like 100Gbps Ethernet hard
IP MAC cores built in; that's some pretty serious stuff.
- Dave