On Oct 14, 2012, at 9:40 PM, Eric Smith wrote:
I wrote:
meeting the maximum leakage current spec is quite
difficult.
Dave McGuire wrote:
Why? (if you want to go into it)
The requirements are basically:
Vol 0.7V max into 70 mA load
Vil max 1.3V
Vih min 1.7V
minimum 5 ns rise and fall times (10% to 90%)
80uA max leakage at 3.8V, 10uA max at 0V (with Vcc from 0.0V to 5.25V)
10pF max capacitance
Qbus is at least a little more forgiving (10uA max at low level seems a
bit odd for TTL, given that it's lower than Iih); drivers have a max
leakage of 25uA at 3.8v, while receivers have a max leakage of 80uA
over their input range. That's not impossible to achieve with some
discrete transistors; a 2N4401 fits the bill nicely for the output
stage (and meets the rise/fall time constraint).
I'd be more inclined to use a FET input stage or possibly even a
comparator to achieve the desired hysteresis and threshold voltage,
though a) I haven't thought about what the impedance effects of the
positive feedback would be, b) I've had a hard time finding good
comparators that work in the correct range and have a short enough
propagation delay, and c) a Schmitt trigger made with discretes is
probably a good enough solution.
I'd love to continue this discussion on or off the list if anyone is
seriously interested in developing new Unibus/Qbus boards. A
standard solution that is easily reproducible would help quite a few
people, I think.
- Dave