Memory/cache on the 11/70

Since there have been a few discussions about the memory/cache of the 11/70 now, I think I might make a few comments as well. When we talk about the MK11 memory, you need to remember that it's a separate memory box, and is not at all transparent to the 11/70. The 11/70 have a memory bus. This memory bus is what you would interface to if you designed your own memory which you put in the free CPU slot. The memory bus don't have any ECC. The ECC of the MK11 is totally located inside the MK11, and is not visible outside. The 11/70 memory bus only have parity bits. So you can skip all the ECC stuff if you want to play with your own memory "box" design. Pretend it's a MJ11 instead, which is simpler. Another detail is that memory refresh is also something that is internal to the box. None of that is visible to the CPU. And neither is memory rewrites in the case of core. Now, my memory of the 11/70 memory bus is fuzzy, since it's been quite a while since I was studying it. But the schematics and manuals are out there, so all of this can be read up on. But as far as I remember, the 11/70 memory bus is rather simple and asynchronous. The machine presents 22 address (actually 24 are defined, but the top two are always zero). You have 32 data bits. 4 parity on data, and probably also parity on address. You have a few control lines, and that's it. You have three types of transactions. Read, Write, and Read-modiy-write. With the 11/74 you also have an interlock function, but I guess that's a moot point since noone around here have an 11/74 CPU anyway. However, the 11/70 cache and memory controller presents quite a lot of overhead and slowdown. If you really would like to speed the 11/70 up (and you can, believe me), you would want to replace the cache and memory controller all together. Now, after reading a few comments here, I've finally understood the relationship between the SETASI PEP-70 and HC-70. The PEP-70 is 4 megs of memory. You can connect that to the 11/70 memory bus. The HC-70 replaces the cache and memory controller in the CPU. This makes the whole 4 Meg of memory look like cache. You hook the PEP-70 to the HC-70 instead. Nice solution actually. I wonder if (in theory) you could hook any memory box to the HC-70, or if the PEP-70 can work in two modes. One as a device on the memory bus, and one as a cache memory for the HC-70. Anyway, if someone were to design a memory system for the 11/70, the way I'd recommend is to go the whole way, since that's where the real gains are. Skip the memory bus and the original cache. The original cache is just 2 KB of 2-way associative memory. If you set up a 4 MB cache, the CPU can run at full steam the whole time, with a cycle time of about 150 nS, if I remember right. It is more complicated, though. You'll have access paths from CPU, Unibus and four massbus controllers to deal with. But it should definitely be doable (heck, SETASI have already done it once). I might be interested in such a project myself, since the 11/70s we have around here still are on MK11 boxes. I could deal with PCBs and design, but I'm very short on time, as usual... :-( No experience at all with FPGAs or any such fancy stuff. Johnny