25 Jul
2014
25 Jul
'14
2:53 p.m.
On Thu, Jul 24, 2014 at 4:21 PM, Tony Duell <ard at p850ug1.demon.co.uk> wrote:
This makes a lot of sense if the mcirocode is in ROM and can't easily be
changed. Having some of the instruction decoding in the hardware speeds
things up and simplifies the microcode. Other machiens with ROM-pased
microcodes do much the same thing (even if it's just the 'not a memory
reference instruciton decode gate' and the ditect contro fo the
accumulator select FF from bit 10 of the iQ register in the HP98x0 CPU.)
The PERQ is one of the few machines that makes no hardwae assumptions
about the machine code instruciton set. So it is equally (in)efficient
and implementing just about anything.
[1] The VAX11/730 also loads the CPU microcode at
power-up, but from what
I rememebr, ther eare some hardware features that optimise it for the VAX
instruction set. While it is possible to give it a differnet instruciton
set, I think it wopuld be a lot less efficient.
All of the microcoded processors DEC designed, whether they had
loadable microcode or only ROM, had hardware that was substantially
oriented toward the normal DEC macroinstruction set(s), and would have The VAX-11/780 introduced the concept of patchable
control store,
where most of the control store was PROM but there was a small amount
of patch RAM. Costs of high speed RAM declined quickly enough that
THe 11/730 uses 200ns DRAMs (!) for the stnadard microcode store. I
didn't beleive it either, but it's in the printset and the tech manual
(both on bitsavers). Ridiculously slow _and_ the CPU has to be halted
every few ms to refresh the control store (the nature fof microdcode is
that it epends a lot of time in small loops, so you can't assume that hte
normal CPU instrucion exectuion will acess enough to the control store to
refresh it). Ho-hum...
-tony