17 Jun
2011
17 Jun
'11
9:55 p.m.
On 17 Jun 2011 at 23:07, Dan Roganti wrote:
I guess another basic way to describe is this way
A positive Logic AND gate is the equivalent to a Negative Logic OR
gate. It's not the bubble input/output OR gate that you see when using
DeMorgan theorem.. So the true state in a AND gate is inverted when
you're using the OR gate.
It's *exactly* the DeMorgan equivalent. One assumes that all logic
levels have a bubble associated with them, so you don't make it
explicit. It's just a convention--"1" can be light off, with
"0"
light on. Or a given phase difference in an AC signal or "1"= tomato
soup and "0"=cream of mushroom. Some of the old databooks (I can't
recall which) used to show logic gates both ways for reference.
Heck, most decent buses (e.g. floppy, Multibus, GPIB) are negative
logic. The control lines on most RAM chips are negative (CS is
usually low-voltage=true along with WR = low, true). I don't see
EE's driving themselves to drink over it. If we'dve created TTL
using PNP transistors instead of NPN, would we be having the opposite
discussion?
Another example is the SR latch
These days you typically see the NAND gate SR latch.
Where the Q output is set to True state(logic1) using the low input -
assert logic O This is still postive logic , but with inverted
assertion level on the inputs Before when the first IC's came about
50yrs ago, you typically see NOR gate SR latches. Where the Q output
is set to True state(logic 0) using a True state/low input - logic 0
again So the NOR SR latch is really a Negative Logic SR latch A very
good example of Negative Logic design is the NASA AGC.
You see NOR logic SR latches in RTL and that doesn't require negative
logic (at least by your "high voltage = true" definition..
you can actually build a XOR gate from only just 4
NAND gates
I hope my skills in ascii schematics are still good (using courier
font)
Yes, but I don't see what that has to do with the thread. If you're
going to dedicate a whole quad NAND package to a single 2-input-XOR,
that's not terribly efficient. Although probably every undergrad
computer logic professor has pointed out this "neat trick" in class
for the last 40+ years, I don't believe it's glitchless, so it's not
a really good choice.
--Chuck