2 Jun
2009
2 Jun
'09
6:53 a.m.
----------------------------------------
Date: Mon, 1 Jun 2009 17:52:46 +0200
From: holger.veit at iais.fraunhofer.de
To:
Subject: Re: Interfacing a 68000 to RAM
dwight elvey schrieb:
Hi
Thanks for the pointers guys. I should have given more information.
It is SRAM and it is fast SRAM 55ns. It is a real 68000 8MHz.
It seens that most seem to prefer the DTACK method over the synchronous one. Is faster or
just more versitle?
What I'm doing is to try to find the best way to connect
to my Canon Cat.
At the Information Apliances Inc they had a daughter board
that they had 128k words of RAM on (256kb).
It was used to recompile the ROM code for the Cat. My understand
is that it had a read/write address of A00000H while there
was a switch to allow it to shadow the ROM at 00H.
I don't think I need the shadow capability since I'd be happy
to just create ROM images.
I'm of course looking for a way to do this with a minimum
of cuts and hacks. I'd prefer to do this with just added
sockets and wires.
There are 2 empty 28pin locations that were intended for ROMs
that I can get most of the address and data lines from
but the parts I have are 32pin. I'll be stacking machine
pin sockets and removing the pins from the lower one
where I'll need to change or jumper to something else.
There is one CE* strobe from the ASCIs inside that I
might be able to use, so long as they didn't include
the LDS signal in its decoding. For these ROMs, they
treated them as byte sources. This ROM enable was
for extended spell checking dictionary. Doing this
has the advantage that the handshake to the CPU
is already done and doesn't require added circuit.
The disadvantage is that it is at 240000H instead
of A00000H, requiring some code change.
If this doesn't work, I'll need to hijack the address
and controls earlier. I'll need to at least cut
into either the DTACK or the VPA line to add my
own signal.
I've been ohming these lines in a powered down circuit
and it looks like they have about a 1K pulup on them
but there is no pulup resistor seen on the board,
by tracing the lines.
I can only figure it must be inside the ASIC. If
it is a O.C. line, I can just force it low without
having to cut. If it is a full pushpull, I'll need
to cut the wire.
I do have a plan for how I might also do the shadowing.
I can mount the system ROMs on machine sockets and
devert the CE* signals. It is in the same area as
the location I expect to mount the additional RAMs.
The data lines are unbuffered to the 68000 so it
should work.
First things first, get it to see the added RAM.
I should mention that we have source code for the
latest ROM version.
Dwight
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Hi
Does anyone have a nice pointer to a diagram
of how the 68K bus is to be connected to RAM?
I not that familiar with all the various signals.
I've spent some time searching but maybe don't
have the right search string.
Dwight
Google search string may be "68000 schematics", and it will point to the
first link
of "68k Single Board Comupter" from "....ac.th" which hides the
interesting part
in a CPLD, but the second link will lead to a detailed PDF
http://www.chiark.greenend.org.uk/~theom/electronics/has/ha68ksys.pdf
which describes the stuff.
Basically, you can derive the relation of UDS, LDS, R/W, AS and DTACK
from the
data sheet, for interfacing RAM the trick part is just the generation of
DTACK;
as long as CPU clock and RAM access time is known, it is a straight forward
wait state circuit.
--
Holger