Motorola M88K books & user manuals (looking for)

yup. I am a 68k programmer so I know what you mean. the 68k is more comfortable to be programmed in assembly, and even the EA modes (especially in the 68020 and CPU32) help a lot. unfortunately, the 68K is very complex to be designed, and the first 68020 used microcode, which is a no-go for modern designs. Arise-v2 comes doesn't have auto incrementer/post decrementer (aka push pop and like), the EA model is basically minimalistic, but we have a special instruction called "SLAC" which is extremely useful for accessing a matrix's cell SLAC means shift left and accumulate in a matrix, a cell is usually accessed by a similar construct, so we have EA = slac .... load/store EA ... yes, our demos will use a lot of matrices and convergences. Just for fun. For sure Arise-v2 will be implemented on a Spartan6 board clocked at 50Mhz for the core and 99Mhz for the DRAM controller, and won't use the pipeline: it will be a multicycles not-pipelined CPU. This because the pipeline introduces a lot of hazards that need to be solved, and this will be our "phase two". First, we need to design and test the ISA on a software simulator in order to check if it's coherent, then, once the ISA is stable, we will put it into a simple hardware implementation, and at that point, we will be able to design a branch prediction etc. Arise is a "learning toy", anyway. All the serious job is done on the RISC-V. On DTB we have a list of RISC-V boards for all the tastes and different costs: ... RISC-V on ASIC chip, RISC-V on FPGA, etc ... (1) http://www.downthebunker.xyz/wonderland/reloaded/bazaar/viewtopic.php?f=3&a… We will try to keep the list updated. Probably someone on our team will also buy a RISC-V board. Currently, we are all working on simulators. thanks!