Z-80 code question about a loop that depends on the contents of the refresh register

The type of RAM shouldn't matter (provided it works properly...) The R register is an 8 bit register. It can be loaded from the accumulator and read back into the accumulaotr (the LD A,R instruction you see here). The bottom 7 bits of R are incremented (with wraparound from 111 1111 to 000 0000) after every instruction. The top bit is left alone. At certain times, the RFSH/ signal is asserted by the Z80, At this point all 8 bits of the R register appear on the bottom 8 bit of the address bus. (As an aside, the I register, the interrupt vector register, appears on the top half of the address bus). Ths incrementing 7 bit address is useful for refreshing those DRAMs that need 128 refresh cycles (a so-called '7 bit refresh'). There is no reason you have to use it for that, even if you have DRAM (you could make your own RAM controller, with its own refresh generator, in fact I would guess a lot of S100 RAM boards did, so they could be used with CPUs other than the Z80). The behaviour of the R register is, of course, unchanged whether you use it for RAM refresh or not. It is my guess (without looking at the datasheets) that as the LD A,R instruction has been said to affect the sign and zero flags that these behave in the obvious way. Z is set if the value loaded is zero. The sign bit is set if the high bit of R is set. If that guess is right then there is a problem. If the high bit of R is set then the routine as given will go into an infinite loop. Remember the automatic incrementing of R is only on the bottom 7 bits. What I need to do is find exactly how the flags are set by the LD A,R -tony