DiscFerret: First working hardware, firmware and microcode!

Al wrote: A possible problem with such drives (including ESDI, SMD, etc.) is that the read gate from the controller to the drive needs to transition to the active state at the right time (during a PLO sync field), or the data separator may lock out-of-phase to the MFM data. In other words, it may think that clock pulses are data pulses and vice versa. Whether this happens depends a lot on the design of the drive electronics. This makes it a pain to dump all the bits on a track at once, when you don't have a priori knowledge of the track format, because you can't just assert read gate continuously and get good NRZ data from the drive. Even when you get good data for one sector, the data separator can lose sync at the write splice between that sector and the next ID field, resulting in reading incorrect data for the following sector. Eric