Brad Parker wrote:
Jim Battle wrote:
Tieing two threads together, he wasn't
against testability of the system
-- the u370 was big on RAS -- but rather he thought functional
verification of the chip was the hard but right way to do things.
no argument from me (I plan to go get the book - does he talk about the
nano code?), but i'd add there's no substitute for good baseline
simulation also.
Just got done finding a problem in a fpga (bus clash) which should have
been caught in simulation but instead passed all the simple functional
tests and only crashed during full-up testing with the linux kernel.
(and naturally everyone blamed the linux kernel :-) 'cept me)
-brad
A tiny bio of him:
http://www.vintage.org/2004/main/bio.php?id=72
The book on amazon (out of print):
http://www.amazon.com/gp/product/0135822971/002-4455590-2956861
The technical detail gets to a very low level, going through specific
PLAs. The real value, though, is that he kept a journal as the project
developed, and he divulges a lot of interesting details, such as the
staffing timeline, project politics and setbacks, the reasoning behind
certain design choices -- basically a lot of the whys and not just the
hows. On the other hand, don't think that the book is going to give you
sufficient information to clone the chip! Certain things he goes into a
length, others get skimmed in order to keep the book a reasonable size.