16 Jan
2013
16 Jan
'13
1:33 a.m.
On 15/01/13 11:48 AM, Pete Turnbull wrote:
On 15/01/2013 02:53, Toby Thain wrote:
Yes I have the spec.
--Toby
On 14/01/13 1:02 PM, Pete Turnbull wrote:
I can't remember where it is, but at least one of the QBus documents
describing bus cycles details which signals are active at what times,
including how and when a DMA request can be ack'd. It might be in one
of the processor handbooks.
On 14/01/2013 16:42, Dave McGuire wrote:
Can you give me a reference on that or more detail? >> Is that true of Qbus, though? I thought
a memory cycle monopolises
>> the bus.
>
> I _think_ you're right, but, as I wrote,
Mouse is right.