Noob analog question (no doubt simple)

Trying to help out some folks on the cbm hackers list read the 6500/1 ROM in the 1520 plotter. It turns out, based on the data sheet, there is a way to put the CPU in a "test" mode and send opcode data to the CPU, and we are going to try to to use that to read the contents of the ROM. The test mode is engaged by placing 10V on the RESET pin. And, you know, before tonight, I thought I was at least average on transistor theory and application, but I'm stumped, and I'm hoping someone can help. To support 3 voltages on RESET (0,5,10), I placed a 2n3904 with the collector on the RESET pin, and emitter on ground. base is biased via 10K resistor to an IO pin on an AVR uC I am using the drive the CPU. That works fine. TO support putting 10V on the RESET, I built a PNP/NPN pair. PNP has E on 10V, C on RESET, and B is biased via 10K to C on NPN. B on NPN is biased via 100K to another IO pin, and E is at GND. The thought was that driving the IO pin high, the NPN will pull the PNP base to ground, thus turning on the PNP, and placing 10V on RESET. And, it works, but it "fades". Over 2ms, RESET slow falls from 10V to ~6V. If I turn the transistor off and then back on, the cycle repeats. So, I obviously am doing it wrong, but I can't seem to determine where my theory fails me, and I thought someone on here could help (or suggest another simple way to support 3 voltages on the RESET pin under SW control. Jim -- Jim Brain brain at jbrain.com www.jbrain.com