Z80 TRAP and CP/M

On 4/4/2006 at 5:28 AM Don Y wrote: There's already an 8259 for handling device interrupts, so I need something that's higher priority than that. That leaves the RST 5.5, 6.5 and 7.5 pins. Given that only one of them (7.5) is edge triggered and not level-triggered, I'll use that one. Right about now you're probably asking yourself--Z80 TRAP, 8259 PIC, RST 7.5 pin?!? What the heck has this guy been smoking? Everyone knows that Z80 timings are wrong for an 8259. And where is this RST 7.5 pin he's talking about? Well, this isn't a Z80--it's an NSC800--sort of a CMOS Z80 with 8085 timings and a multiplexed data/address bus like the 8085. I'm retrofitting one into an 8085 box--there are a number of Z80-only programs that I'd like to use and the National chip appears to be the most straightforward way to do this. The pinout is substantially different from an 8085 and there are a couple of signals that need to be inverted, but the timing charts look good--and my particular application doesn't have the CPU making use of SID or SOD or the undocumented 8085 instructions. The hardest part was finding a supply of the NSC parts. Cheers, Chuck