8 Sep
2013
8 Sep
'13
8:53 p.m.
I think perhaps that you do not understand how a PLL
really operates.
In every case that I've ever worked with, the PLL center frequency is a
multiple of the reference. (That, for example, is why having a 3GHz CPU
clock on your personal computer that the reference frequency is always
much lower than that 3GHz.
well, this is not completely correct... basic PLL does simple integer
multiplication,
but higher complexity PLLs could include dividers with variable module, or
even
more complex modern PLLs use a sort of "noise shaping" to achieve a
frequency
multiplication by N.M, where N is integer part, M is fractional part, often
with a
length of 16 or 24 bits...
I'm not talking about post-dividers, the VCO really works at the fractional
frequency.
By the way, a quite simple PLL 4x with a post-divider x3 could do the job.
PLL will try to keep aligned the edges of the reference signal with the
edges of the regenerated signal; but not all the edges could be aligned at
the same time,
because the frequency ration is not integer.
We have a situation like this, without a proper signal to reset the PLL
counter always in the same disc position, PLL will align randomly in one of
the following ways (number is a pulse, - is stable signal):
original 12 sector:
---0---------------1---------------2---------------3---------------4---------------5---------------6---
case 1 16 sector (0, 3, 6, etc are aligned):
---0----------1-----------2-----------3-----------4-----------5-----------6-----------7----------8---
case 2 16 sector (1, 4, 7, etc are aligned):
-------N-----------0----------1-----------2-----------3-----------4-----------5-----------6----------7---
case 3 16 sector (2, 5, 8, etc are aligned):
----------N-----------N-----------0----------1-----------2-----------3-----------4-----------5------
Of course the random choice of the pulse that will be aligned could let the
regenerated sector position shift by 1/3 of 2/3 of the original 12-sector.
Slots in the hub ring.
There are actually 13 and 17, one extra midway between the 12'th and
1'st for the index.
Ah-haaa! THAT added pulse should be used to solve the phase alignment
uncertain, thus starting to align always with the first sector!
Beside the digital implementation using microprocessors, that would have
an implicit problem of delay, cause by software latencies,
I would prefer a true PLL implementation, with a VCO driven at 4N the
reference signal, and a post-divider by 3N. As frequency of the pulses is
quite low,
a VCO working at higher frequency (always multiple of 4) could be preferable
for component choice, and a bigger divider (correspondent multiple of 3)
could
reduce the amount of jitter and offer a faster lock time.
The circuit could be simply realized using a 4046 CMOS as PLL/VCO and
a couple of dividers like 4040, 4024.
Andrea