OT: how big would it be?

These days, no one would seriously attempt to build a CPU equivalent using TTL SSI/MSI components simply because the packaging gets too much in the way of smooth data flow. I once built a 650x CPU equivalent on a 4"x6" wirewrap board using TTL SSI/MSI, but it was my goal to build one using the logic available to the original designers. That was not easy, but it fit only because of the efficiencies inherent in the 650x series timing and instruction set. If one were to do the same thing with an 8080 CPU design, I suspect it could be forced to fit on a board like an S-100 card. It might be difficult to do in "period" family logic, i.e. with the parts that were available to the designers of the 8080, though. If you'd like to convince yourself of this, take a look at the '72 TTL data book from T.I. or Signetics. If one were limited to 28-pin FPLD's and smaller, I think it could be done easily enough. That would take the emphasis off parts search and the occasional unavailability of some functions, while allowing some random logic to be localized in a single device rather than requiring several different flavors of AOI gates, expanders, etc. The internal data paths of the 8080 could more easily be done with today's tristate devices than back in '72-'74 with muxes of various types. There are FPGA cores, though . . . I personally think it would be fun to build an S-100 card to replace the 8080 LSI. It might well be possible to replace all the external support logic with the hardware that goes "inside" the device, and you could fiddle with the instruction set more or less like the folks with wire-wrapped PDP8 processors did from time to time. Dick -----Original Message----- From: Eric Smith <eric(a)brouhaha.com> To: Discussion re-collecting of classic computers <classiccmp(a)u.washington.edu> Date: Wednesday, October 20, 1999 12:25 AM Subject: Re: OT: how big would it be?