22 Nov
2019
22 Nov
'19
2:30 p.m.
2. When doing 18bit on UNIBUS-A we put all kind of
signal levels
on parity lines PA,PB = DATA<16:17>.
Won't the KS10 CPU interpret these as real BUS parity errors generated
by some UNIBUS-A device?
I asked nonsense here: if UNIBUS-A is 18bit too, no parity will be evaluted of course.
Joerg