29 Nov
2011
29 Nov
'11
12:44 a.m.
On Nov 28, 2011, at 2:19 PM, Richard wrote:
Absolutely. For something newer, like a VAX with the direct memory bus (I haven't
actually looked at it, so I may well be wrong), it should be fairly simple. For
UNIBUS/QBUS boards (including PMI, as far as I know), the drivers for 120-ohm
open-collector buses are a bit of an issue. You can hack them together with 74AS641 and
74AS760, but I haven't done much testing on either of these to see if they're
reasonable for actual buses (especially really long ones). The thresholds on them are
also not 100% compatible with the DEC standard, though they'll probably do for most
real-world situations.
One of these days, I need to make up a simple test board to stick in my backplane to run
some simple bus compatibility tests. There was a thread either here or on comp.sys.dec a
while ago about some other possible ICs with built-in series terms which looked
interesting... anyone remember what they were?
- Dave
I'm not
well versed in memory design, but you might get it to work with
some buffer circuitry that kept the memory refreshed properly, even if it's
doing nothing for 7 out of 8 cycles.
Yes, sorry I wasn't explicit about what sort of design I was
imagining. I was definitely feeling that there would need to be some
sort of controller on the memory board that mediates between the host
and the modern memory parts -- something to match the timings between
the two worlds.
I wasn't thinking that just hooking the modern chips up straight to
the vintage busses was going to do the trick.