24 Aug
2021
24 Aug
'21
5:50 a.m.
On Tue, Aug 24, 2021 at 11:38:42AM -0400, Paul Koning wrote:
Not at all surpised.
That was later done formally in the ColdFire processor. They removed all the
CISCy instructions replacing them with macros and left the RISCy instruction
set.
> On Aug 24, 2021, at 6:34 AM, Diane Bruce <db at db.net> wrote:
>
> On Mon, Aug 23, 2021 at 09:09:55PM -0400, Paul Koning via cctalk wrote:
>>
>>
>>> On Aug 23, 2021, at 8:38 PM, Tom Stepleton via cctalk <cctalk at
classiccmp.org> wrote:
>>>
...
faster if one
just did them with the 'normal' instruction set.
Not too surprising given that the instruction worked 4 bits at a time while a reasonable
software implementation goes 8 bits at a time.
The more general point is one I learned on the Moto 68040. The task was to write a fast
packet forwarding module (for an FDDI -> Ethernet switch, wihch ended up being the
DECswitch 900). When I studied the instruction timings I realized the "RISC
subset" of the 68040 instruction set and addressing modes runs in one or two cycles
per instruction, while all the other cases take a great deal more. So I wrote it in the
RISC subset, and ended up processing 60k packets per second, in a 25 MHz processor.
paul
Diane
--
db at FreeBSD.org db at db.net http://www.db.net/~db