18 Aug
2006
18 Aug
'06
3:59 p.m.
On Aug 18, 2006, at 4:54 PM, Tony Duell wrote:
Well let's put it this way. I was the sixteen-year-old kid coming in
to wire-wrap and test after school, and the two Princeton University
professors were the ones doing the design. Many people suggested
heavier bypassing, but were smacked down at every turn, and "everybody
knows the PhDs know better!" *spit*
-Dave
--
Dave McGuire
Cape Coral, FL
From 1986
to early 1988 I worked on the Navier-Stokes Supercomputer
Project at Princeton University. Each node of that machine had four
4MW memory planes (36-bit word) built from 41256 chips; 576 chips per
memory plane, handled by a pair of Intel 8207 DRAM controllers. We
had
really nasty problems with the refresh cycles creating tons of noise
on
the Vcc bus. Man that was a nightmare; it took weeks to get it
cleaned
up. If I recall correctly we wound up rebuilding the boards with a
bypass capacitor for every DRAM chip.
Which you darn well should have fitted in the first place!. As I've
said
many times 'Decoupling capacitors are cheap, my time in finding
glitches
is not'. OK if you're going into production it _might_ be worth saving
a
few pence by eliminating unnecessary capacitors. But for a prototype,
fit at least one per chip. Period.