Fairchild SYMBOL

Al Kossow wrote: Very cool. Do you know if it is the complete machine? Any schematics? How large is it? It makes me wonder if it could be implemented on an FPGA. With today's design languages, it wouldn't be very difficult to create a tool chain that could turn a BNF description into a netlist -- BNF -> verilog, verilog->gates. I'm sure one thing that was very daunting back then was any small change to the language would result in massive changes to the wiring. Of course there would be no reason for carrying it out, but it is fun to think about. Even if you could build such an FPGA and got it going at 100 MHz, it would still be slower than a conventional compiler running on a 2 GHz x86. Despite the increased efficiency, it is hard to bridge that 20x clock multiplier. The best you could do is improve on the start up time, but for any code that iterated, the compiler would win as the parsing costs are paid only once.