13 Sep
2004
13 Sep
'04
4 p.m.
Bill Sudbrink may have written:
Another data point plus an "Arg!"...
Ohio Scientific was quite fond of 2114s (Arg!). It looks like
the cause of the power supply failure in my C4P is that one of
the 24K memory cards (48 2114s) was drawing well over spec, even
though it appeared to be providing reliable memory operation. It
was populated with the LC (low power CMOS) 2114 chip. According
to specs on the web, these should draw 40 milliamps max. I pulled
10 at random. Not one pulled less than 70. Now, I tested them
with all pins floating other than power and ground and I wonder
how much difference that makes, but totaling up an average of 75
per chip gives about what the card as a whole draws when in
operation. The other card, populated with another vendors 2114s,
draws over 1/2 amp less when in operation, reflecting about 42
milliamps per chip.
When I was designing I/O boards for spaceborne computers I once saw
what happens when most inputs are left floating on CMOS designs. This
was a design full of (~30) 54HCxx ICs. When powered up, the boards
power consumption varied wildly from almost nothing to way above
spec. You could play the power consumption by waving your hands
above the board.
Thim makes me conclude that in order to correctly measure stand
by current consumption on any CMOS circuit, you _must_ tie all
unused inputs to either Vdd or Vss, whichever makes most sense.
If the input of a CMOS inverter is left floating, there is a good
chance it will stay somewhere in the middle between high and low and
both transistors will be half open for current to flow all the way
from Vdd to Vss. If the input is tied to Vdd or Vss,
then at least
one of the transistors will be shut off, and very little current
will flow. This is all there is to CMOS low static current con-
sumption.
Thank you for listening.
/Ulf Andersson
Veteran computerist in spe.